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Practical FPGA DSP with Xilinx IP cores (FIR, CIC, DDS, FFT): from simulation to real-time deployment on Zynq 7000
What you'll learn
How to Simulate Xilinx DSP IP cores (FIR, CIC, DDS compiler and FFT) in Vivado with Verilog testbenches & Python analysis
How to Integrate IP cores into FPGA designs on development board
How to Develop standalone embedded C application to interface with DSP IP cores
How to Automate Vivado & Vitis workflow with TCL and Python scripts
Requirements
Vivado 2024.2
Vitis 2024.2
Python >= 3.0
Powershell
Any development board with Zynq 7000 SoC (Arty z7-20 as example)
VISITOR COMMENTS (0 )
FILE LIST
Filename
Size
~Get Your Files Here !/1 - Introduction/1 -Introduction.mp4
41.9 MB
~Get Your Files Here !/1 - Introduction/2 -Requirements and Workflow Automation.mp4
115.4 MB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/auto/clean.py
1.8 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/auto/gui_launcher.py
2 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/auto/run_sim.py
2.3 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/auto/run_vitis.py
2.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/auto/run_vivado.py
2.5 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/common/dds_axi_wrapper.v
2.2 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/common/tb_util.vh
7.3 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/create_vitis.py
1.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/dsp_sim.tcl
13.3 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_cic/cic_main.c
6.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_cic/tb/cic_compiler_tb.v
3.9 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_cic/tb/cic_compiler_tb_behav.wcfg
4 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_cic/tcl/cic_hw.tcl
1.8 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_cic/tcl/cic_sys.tcl
45.9 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_dds/dds_main.c
7.2 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_dds/tb/dds_compiler_tb.v
5.6 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_dds/tb/dds_compiler_tb_behav.wcfg
20.6 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_dds/tcl/dds_hw.tcl
2 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_dds/tcl/dds_sys.tcl
45.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/coe/BPF.coe
237 B
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/coe/hilbert_0.coe
757 B
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/coe/LPF_dec.coe
237 B
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/coe/LPF_int.coe
237 B
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/fir_main.c
8.8 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/tb/fir_compiler_tb.v
7.8 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/tb/fir_compiler_tb_behav.wcfg
11.9 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/tcl/fir_hw.tcl
1.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_fir/tcl/fir_sys.tcl
47.2 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_xfft/tb/xfft_tb.v
5.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_xfft/tb/xfft_tb_behav.wcfg
28.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_xfft/tcl/xfft_hw.tcl
1.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_xfft/tcl/xfft_sys.tcl
41.1 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/ip_xfft/xfft_main.c
9.3 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/py/cic_compiler.py
3.5 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/py/dds_compiler.py
4.9 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/py/fir_compiler.py
4.1 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/py/xfft.py
5.7 KB
~Get Your Files Here !/1 - Introduction/udm-dsp-xilinx/README.md
2.1 KB
~Get Your Files Here !/2 - Xilinx DSP IP cores simulation/1 -Vivado Simulation FIR compiler v7.2.mp4
311.7 MB
~Get Your Files Here !/2 - Xilinx DSP IP cores simulation/2 -Vivado Simulation CIC compiler v4.0.mp4
138.4 MB
~Get Your Files Here !/2 - Xilinx DSP IP cores simulation/3 -Vivado Simulation DDS compiler v6.0.mp4
122.5 MB
~Get Your Files Here !/2 - Xilinx DSP IP cores simulation/4 -Vivado Simulation Fast Fourier Transform v9.1.mp4
114.8 MB
~Get Your Files Here !/3 - Development C application to interface with Xilinx DSP IP cores on Zynq 7000/1 -Zynq 7000 SoC development C application to interface with FIR compiler IP cores.mp4
341.5 MB
~Get Your Files Here !/3 - Development C application to interface with Xilinx DSP IP cores on Zynq 7000/2 -Zynq 7000 SoC development C application to interface with CIC compiler IP cores.mp4
298.6 MB
~Get Your Files Here !/3 - Development C application to interface with Xilinx DSP IP cores on Zynq 7000/3 -Zynq 7000 SoC development C application to interface with DDS compiler IP cores.mp4
224.3 MB
~Get Your Files Here !/3 - Development C application to interface with Xilinx DSP IP cores on Zynq 7000/4 -Zynq 7000 SoC development C application to interface with FFT IP core.mp4
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