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TORRENT DETAILS

[FreeTutorials.Us] Udemy - Learn VHDL And FPGA Development

TORRENT SUMMARY

[FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

Status:

This torrent has NOT been verified.

Category:

Other

Infohash:

de3d7c39abbbce16fea5e882b0152398cff8c485

Size:

2 GB in 99 files

Release Date(s):

Torrent Release: 29-09-2018 by user

Swarm:

0 Seeds & 1 Peers

Vote:

Current vote: 1

DESCRIPTION

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FILE LIST

Filename		Size
	10. Xilinx Tools/1. Xilinx Tools Introduction.mp4	1.3 MB
	10. Xilinx Tools/1. Xilinx Tools Introduction.srt	1.3 KB
	10. Xilinx Tools/1. Xilinx Tools Introduction.vtt	1.1 KB
	10. Xilinx Tools/1.1 Digilent Inc. - Digital Design Engineer's Source.html	208 B
	10. Xilinx Tools/1.2 Xilinx ISE Download.html	158 B
	10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.mp4	36.9 MB
	10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.srt	8.9 KB
	10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.vtt	7.8 KB
	10. Xilinx Tools/3. ISim VHDL Simulation Tool.mp4	4.7 MB
	10. Xilinx Tools/3. ISim VHDL Simulation Tool.srt	2.6 KB
	10. Xilinx Tools/3. ISim VHDL Simulation Tool.vtt	2.3 KB
	10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.mp4	9.2 MB
	10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.srt	8.8 KB
	10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.vtt	7.7 KB
	10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.mp4	1.8 MB
	10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.srt	2 KB
	10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.vtt	1.8 KB
	10. Xilinx Tools/6. Xilinx Tools.html	163 B
	11. Lab 1 - Full Adder/1. Introduction.mp4	5.7 MB
	11. Lab 1 - Full Adder/1. Introduction.srt	2.3 KB
	11. Lab 1 - Full Adder/1. Introduction.vtt	2 KB
	11. Lab 1 - Full Adder/1.1 Lab-1.zip.zip	6.8 KB
	11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4	87.9 MB
	11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.srt	19.5 KB
	11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.vtt	17.1 KB
	11. Lab 1 - Full Adder/3. BASYS 2 Full Adder Demonstration.mp4	31.9 MB
	11. Lab 1 - Full Adder/3. BASYS 2 Full Adder Demonstration.srt	2.4 KB
	11. Lab 1 - Full Adder/3. BASYS 2 Full Adder Demonstration.vtt	2.1 KB
	11. Lab 1 - Full Adder/4. BASYS 2 Full Adder Solution.mp4	38.7 MB
	11. Lab 1 - Full Adder/4. BASYS 2 Full Adder Solution.srt	17.5 KB
	11. Lab 1 - Full Adder/4. BASYS 2 Full Adder Solution.vtt	15.3 KB
	12. Lab 2 - Shift Register/1. Introduction.mp4	5.7 MB
	12. Lab 2 - Shift Register/1. Introduction.srt	2.6 KB
	12. Lab 2 - Shift Register/1. Introduction.vtt	2.3 KB
	12. Lab 2 - Shift Register/1.1 Lab-2.zip.zip	6.2 KB
	12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4	46.9 MB
	12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.srt	2.4 KB
	12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.vtt	2.1 KB
	12. Lab 2 - Shift Register/3. BASYS 2 Shift Register Demonstration.mp4	37.7 MB
	12. Lab 2 - Shift Register/3. BASYS 2 Shift Register Demonstration.srt	4.7 KB
	12. Lab 2 - Shift Register/3. BASYS 2 Shift Register Demonstration.vtt	4.2 KB
	12. Lab 2 - Shift Register/4. Shift Register Completed Design.html	1.7 KB
	13. Lab 3 - Universal Shift Register/1. Introduction.mp4	5.1 MB
	13. Lab 3 - Universal Shift Register/1. Introduction.srt	2.2 KB
	13. Lab 3 - Universal Shift Register/1. Introduction.vtt	1.9 KB
	13. Lab 3 - Universal Shift Register/1.1 Sim_Mem_Init.zip.zip	23.6 KB
	13. Lab 3 - Universal Shift Register/1.2 Lab-3.zip.zip	61.5 KB
	13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4	70.6 MB
	13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.srt	4.7 KB
	13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.vtt	4.1 KB
	13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4	62.3 MB
	13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.srt	8.2 KB
	13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.vtt	7.2 KB
	13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4	69.6 MB
	13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.srt	27.7 KB
	13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.vtt	24.1 KB
	13. Lab 3 - Universal Shift Register/5. Universal Shift Register VHDL Design.html	2.1 KB
	14. Lab 4 - 7 Segment Display/1. Introduction.mp4	6.1 MB
	14. Lab 4 - 7 Segment Display/1. Introduction.srt	2.6 KB
	14. Lab 4 - 7 Segment Display/1. Introduction.vtt	2.3 KB
	14. Lab 4 - 7 Segment Display/1.1 Lab-4.zip.zip	12.2 KB
	14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4	43.8 MB
	14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.srt	2.6 KB
	14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.vtt	2.3 KB
	14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4	45.4 MB
	14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.srt	5.9 KB
	14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.vtt	5.1 KB
	14. Lab 4 - 7 Segment Display/4. Hexadecimal to 7 Segment Display VHDL Design.html	8.8 KB
	15. Lab 5 - Counter/1. Introduction.mp4	3.7 MB
	15. Lab 5 - Counter/1. Introduction.srt	1.6 KB
	15. Lab 5 - Counter/1. Introduction.vtt	1.4 KB
	15. Lab 5 - Counter/1.1 Lab-5.zip.zip	7.6 KB
	15. Lab 5 - Counter/2. BASYS 3 Counter Demonstration.mp4	24.7 MB
	15. Lab 5 - Counter/2. BASYS 3 Counter Demonstration.srt	3.1 KB
	15. Lab 5 - Counter/2. BASYS 3 Counter Demonstration.vtt	2.7 KB
	15. Lab 5 - Counter/3. BASYS 2 Counter Demonstration.mp4	31.4 MB
	15. Lab 5 - Counter/3. BASYS 2 Counter Demonstration.srt	3.5 KB
	15. Lab 5 - Counter/3. BASYS 2 Counter Demonstration.vtt	3.1 KB
	15. Lab 5 - Counter/4. Counter VHDL Design.html	4.3 KB
	16. Lab 6 - Multiplier/1. Introduction.mp4	7.6 MB
	16. Lab 6 - Multiplier/1. Introduction.srt	3.3 KB
	16. Lab 6 - Multiplier/1. Introduction.vtt	2.9 KB
	16. Lab 6 - Multiplier/1.1 Lab-6.zip.zip	61.8 KB
	16. Lab 6 - Multiplier/1.2 Lab 6 Multiplier.pdf.pdf	777.7 KB
	16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4	102.4 MB
	16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.srt	6 KB
	16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.vtt	5.3 KB
	16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4	61.9 MB
	16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.srt	6.6 KB
	16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.vtt	5.7 KB
	16. Lab 6 - Multiplier/4. Multiplier VHDL Design File.html	7.5 KB
	17. Lab 7 - RC Servo/1. Introduction.mp4	21.3 MB
	17. Lab 7 - RC Servo/1. Introduction.srt	15.7 KB
	17. Lab 7 - RC Servo/1. Introduction.vtt	13.9 KB
	17. Lab 7 - RC Servo/1.1 Lab-7.zip.zip	14.7 KB
	17. Lab 7 - RC Servo/1.2 3.0V to 5.0V Schematic_schem.pdf.pdf	284.7 KB
	17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4	81.6 MB
	17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.srt	5.4 KB
	17. Lab 7 - RC Servo/2.1 RC_Servo.zip.zip	624.2 KB

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