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Language: English | Size: 572 MB | Duration: 3h 28m
VLSI - Essential timing checks
What you'll learn
Understand various STA checks for timing closure
Able to do a quality analysis for real designs
Know-how on how real STA works in industries, something which you will not find in any books
Step-by-step and structured timing analysis
Requirements
Knowledge on physical design flow will be good to have
If not, no worries. This course will take you from basics to advanced in a structured manner and create an interest in physical design world
Description
Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.
Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations
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FILE LIST
Filename
Size
~Get Your Files Here !/01 - Introduction and agenda/001 Introduction.mp4
6.1 MB
~Get Your Files Here !/01 - Introduction and agenda/001 Introduction_en.vtt
3.7 KB
~Get Your Files Here !/01 - Introduction and agenda/002 Introduction to timing path and arrival time.mp4
21.5 MB
~Get Your Files Here !/01 - Introduction and agenda/002 Introduction to timing path and arrival time_en.vtt
11.2 KB
~Get Your Files Here !/01 - Introduction and agenda/003 Introduction to required time and slack.mp4
24.6 MB
~Get Your Files Here !/01 - Introduction and agenda/003 Introduction to required time and slack_en.vtt
10.6 KB
~Get Your Files Here !/01 - Introduction and agenda/004 Introduction to basic categories of setup and hold analysis.mp4
22.6 MB
~Get Your Files Here !/01 - Introduction and agenda/004 Introduction to basic categories of setup and hold analysis_en.vtt
11.4 KB
~Get Your Files Here !/01 - Introduction and agenda/005 Introduction to data check and latch timing.mp4
29.5 MB
~Get Your Files Here !/01 - Introduction and agenda/005 Introduction to data check and latch timing_en.vtt
10.8 KB
~Get Your Files Here !/01 - Introduction and agenda/006 Introduction to slew, load and clock checks.mp4
36.9 MB
~Get Your Files Here !/01 - Introduction and agenda/006 Introduction to slew, load and clock checks_en.vtt
9.8 KB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/001 Convert logic gates into nodes.mp4
23.6 MB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/001 Convert logic gates into nodes_en.vtt
11.9 KB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/002 Compute actual arrival time (AAT).mp4
27.2 MB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/002 Compute actual arrival time (AAT)_en.vtt
11.8 KB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/003 Compute required arrival time (RAT).mp4
25.8 MB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/003 Compute required arrival time (RAT)_en.vtt
10 KB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/004 Compute slack and introduction to GBA-PBA analysis.mp4
31.9 MB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/004 Compute slack and introduction to GBA-PBA analysis_en.vtt
11.8 KB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/005 Convert pins to nodes and compute AAT, RAT and slack.mp4
34.5 MB
~Get Your Files Here !/02 - First things first - Introduction to timing graph/005 Convert pins to nodes and compute AAT, RAT and slack_en.vtt
12.7 KB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/001 Introduction to transistor level circuit for flops.mp4
21 MB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/001 Introduction to transistor level circuit for flops_en.vtt
10.3 KB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/002 Negative and positive latch transistor level operation.mp4
20.7 MB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/002 Negative and positive latch transistor level operation_en.vtt
10.1 KB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/003 Library setup time calculation.mp4
30.6 MB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/003 Library setup time calculation_en.vtt
10.5 KB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/004 Clk-q delay calculation.mp4
38.1 MB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/004 Clk-q delay calculation_en.vtt
12.1 KB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/005 Steps to create eye diagram for jitter analysis.mp4
21.9 MB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/005 Steps to create eye diagram for jitter analysis_en.vtt
10.5 KB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/006 Jitter extraction and accounting in setup timing analysis.mp4
32.1 MB
~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/006 Jitter extraction and accounting in setup timing analysis_en.vtt
10.2 KB
~Get Your Files Here !/04 - Textual timing reports and hold analysis/001 Setup analysis - graphical to textual representation.mp4
14.5 MB
~Get Your Files Here !/04 - Textual timing reports and hold analysis/001 Setup analysis - graphical to textual representation_en.vtt
10 KB
~Get Your Files Here !/04 - Textual timing reports and hold analysis/002 Hold analysis with real clocks.mp4
10.7 MB
~Get Your Files Here !/04 - Textual timing reports and hold analysis/002 Hold analysis with real clocks_en.vtt
12.6 KB
~Get Your Files Here !/04 - Textual timing reports and hold analysis/003 Hold analysis - graphical to textual representation.mp4
8.4 MB
~Get Your Files Here !/04 - Textual timing reports and hold analysis/003 Hold analysis - graphical to textual representation_en.vtt
9.4 KB
~Get Your Files Here !/05 - On-chip variation/001 Sources of variation - etching.mp4
13.5 MB
~Get Your Files Here !/05 - On-chip variation/001 Sources of variation - etching_en.vtt
13.6 KB
~Get Your Files Here !/05 - On-chip variation/002 Sources of variation - oxide thickness.mp4
10.2 MB
~Get Your Files Here !/05 - On-chip variation/002 Sources of variation - oxide thickness_en.vtt
11.1 KB
~Get Your Files Here !/05 - On-chip variation/003 Relationship between resistance, drain current and delay.mp4
14.1 MB
~Get Your Files Here !/05 - On-chip variation/003 Relationship between resistance, drain current and delay_en.vtt
14.1 KB
~Get Your Files Here !/06 - OCV timing and pessimism removal/001 OCV based setup timing analysis.mp4
14.3 MB
~Get Your Files Here !/06 - OCV timing and pessimism removal/001 OCV based setup timing analysis_en.vtt
12.6 KB
~Get Your Files Here !/06 - OCV timing and pessimism removal/002 Setup timing analysis after pessimism removal.mp4
13.3 MB
~Get Your Files Here !/06 - OCV timing and pessimism removal/002 Setup timing analysis after pessimism removal_en.vtt
11.7 KB
~Get Your Files Here !/06 - OCV timing and pessimism removal/003 OCV based hold timing analysis.mp4
8.4 MB
~Get Your Files Here !/06 - OCV timing and pessimism removal/003 OCV based hold timing analysis_en.vtt
7.3 KB
~Get Your Files Here !/06 - OCV timing and pessimism removal/004 Hold timing analysis after pessimism removal.mp4
14.1 MB
~Get Your Files Here !/06 - OCV timing and pessimism removal/004 Hold timing analysis after pessimism removal_en.vtt
11.9 KB
~Get Your Files Here !/07 - Conclusion/001 Conclusion and next topics!!.mp4
2.5 MB
~Get Your Files Here !/07 - Conclusion/001 Conclusion and next topics!!_en.vtt
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